//baud_rate_clk generate
module tx_bps_clk_gen #(
	parameter CLK_FREQ = 50_000_000 , //hz 
	parameter BAUD_RATE = 9600 
)(
	input wire clk,    // Clock
	input wire rst_n,  // Asynchronous reset active low
	input wire tx_done ,
	input wire tx_start,

	output logic bps_clk 
	
);

	localparam 	BPS_CNT = (CLK_FREQ / BAUD_RATE) - 1  ;
	localparam  BPS_WIDTH=$clog2(BPS_CNT);

	logic[BPS_WIDTH-1:0] cnt ;
	logic c_sta ;	//current state
	logic n_sta ; //next state

	always_ff@(posedge clk or negedge rst_n)begin
		if(~rst_n)begin
			c_sta <= 1'd0 ;
		end else begin
			c_sta <= n_sta ;
		end
	end
	always_comb begin
		case(c_sta)
			1'b0 : n_sta = tx_start ? 1'b1 : 1'b0 ;
			1'b1 : n_sta = tx_done  ? 1'b0 : 1'b1 ;
			default : begin n_sta = 0 ; end
		endcase
	end

	//baud rate clk cnt 
	always_ff @(posedge clk or negedge  rst_n) begin
		if(~rst_n)begin
			cnt <= {BPS_WIDTH{1'b0}} ; 
		end else begin
			if(~c_sta)
				cnt <= {BPS_WIDTH{1'b0}};
			else begin
				if (cnt == BPS_CNT)
					cnt <= {BPS_WIDTH{1'b0}};
				else
					cnt <= cnt + 1'b1 ;
			end
		end
	end

	//bps clk output 
	always_ff @(posedge clk or negedge rst_n) begin : proc_bps_clk
		if(~rst_n) begin
			bps_clk <= 1'b0;
		end else begin
			if(cnt == 'd1)begin
				bps_clk <= 1'b1 ;
			end else begin
				bps_clk <= 1'b0 ;
			end
		end
	end
endmodule : tx_bps_clk_gen

